Technical Field
The present invention generally relates to semiconductor structures with an isolation region under the gate. More particularly, the present invention relates to non-planar semiconductor structures with an isolation region separating the gate from the drain.
Background Information
Non-planar semiconductor devices in high-voltage applications can sustain damage to isolation material in a region under the conductive gate, separating the gate and the drain. Currently, such isolation regions are recessed, allowing the conductive gate to “wrap” around the fin on that side. However, while wrapping the gate around the fin generally is the implementation of current non-planar art, such wrapping near the drain can induce a high local electric field that can degrade the oxide under the gate.
Therefore, a need exists for a way to reduce or eliminate degradation of the gate oxide due to the high local electric field.